1. Field of the Invention
The present invention relates very generally to circuit board fabrication, and pertains more particularly, to an improved electrical printed circuit board construction and associated method of manufacture thereof.
2. Background Discussion
Printed circuit boards are used extensively in the computer hardware field for constructing electronic circuits. FIG. 1 shows a small section of a typical prior art printed circuit board. Normally, chip carriers, only one of which is shown at 150 in FIG. 1, containing electronic components, are placed on top of the printed wiring board 110 so that the pins 151 of the chip carrier 150 contact corresponding copper pads 126 on the top surface of the board. The board itself usually consists of several levels of circuitry including the top layer. FIG. 1 shows only two of the levels, each level of circuitry actually consisting of two separate physical layers, a laminate layer 112, 114 and a pre-preg layer 120, 122. The laminate layers 112, 114 actually contain the electrical conductors on their surface while the pre-preg layers 120, 122 are typically a "B-staged" or partially cured fiberglass reinforced polymer. The laminate layers are imprinted or etched with copper pads and conductors which form the circuit pattern on each level of circuitry. FIG. 1 shows a pad at 126 and a conductor run at 128. The copper etchings provide the connections for electrical communication within each level of circuitry, however, another means is necessary for providing inter level communication. This is accomplished in the prior art by the use of plated through holes illustrated at 111.
The standard procedure is to stack up all the layers of the printed wiring board and to drill holes through the entire stack up wherever an inter-level connection is desired. Therefore, even if an inter-level connection is needed from only one layer to the next (e.g. layer 112 to layer 114 connecting pad 126 to conductor 128), the hole is drilled through the entire stack-up. The hole is then electro-plated with copper during processing in order to provide an electrical conduction path through the hole. In the layers 112 and 114 which are to be electrically connected by the particular hole 111, copper conductors 126 and 128 contact the hole and carry the electrical signals to their source or destination on the given level. Unfortunately, however, in the remaining levels of circuitry, the copper conductors which are carrying signals to and from other sources and destinations must be routed around holes which were created for inter level conductance in other layers.
The use of plated through holes leads to several other problems and disadvantages. First, copper plating, which takes a significant amount of time, must be performed in a separate step during the processing of the printed wiring board. Also, copper has a different expansion rate when heated than the fiberglass polymer which is used in the pre preg layer. Due to this, plated-through holes are susceptible to cracking with temperature fluctuations.
A further disadvantage of plated-through hole technology is that it places an artificial limit on how small the hole diameters can be. This problem arises due to technical considerations concerning the drill bit size and the electroplating step. The drill bit consideration involves what is called aspect ratio. The aspect-ratio is the ratio between the diameter of the drill bit and the thickness of the material that the bit must drill through. The greater the number of layers that the drill bit must drill through per hole, the shorter the life expectancy of the drill. In other words, a drill of a certain diameter used to drill through two layers per hole will be able to drill through more layers overall before breakage than a drill used to drill through twelve layers per hole. The corollary to this fact is that a drill bit used to drill through fewer layers per hole can have a small diameter yet provide the same lifetime expectancy as a thicker drill which is used for drilling a deeper hole.
The second artificial limit on hole size is the electroplating process. Small diameter holes are much more difficult to electroplate than larger ones. The costs of electroplating increase rapidly as hole diameter decreases.
The problem of hole diameter is illustrated in a typical 50 mm pitch board as shown in FIG. 3. The term 50 mm pitch refers to the fact that the distance between the center of adjacent conductors or adjacent pads is 50 mm. On a typical 50 mm pitch board, the copper pads which provide contacts for the pins of chip carriers are very small, approximately 20 mm by 35 mm. The circuit board designer is faced with the choice of high electroplating costs as well as using a very small diameter drill bit that will need to be replaced frequently or finding some way to provide for larger holes. What is normally done is that a copper conductor 80 is etched on to the board 81 leading from the copper pads 82 to plated-through holes 84 which are placed elsewhere on the board where there is enough room to place the holes on a 100 mm pitch. This is called fanout. Often, the designer makes a compromise in which only half of the pads are fanned out to a 100 mil pitch. The fanned out holes typically have a 35 mm diameter. The remaining holes have diameters of approximately 18 mm and are drilled through every other pad thereby providing holes on a 100 mm pitch. With fanout, not only do the larger holes take up more routing space than is necessary but the copper etches leading from the pad to the holes also occupy valuable routing area. In addition, fanout adds signal length which increases propogation delay as well as noise (cross-talk) vulnerability.
A further disadvantage of the use of larger holes is the fact that fewer etched conductors can be routed between holes. For instance, whereas on a typical 50 mm pitch board, one or two conductor paths can be routed between holes, this number might be increased to three or four copper conductors if not for the artificial limitation on hole diameter. The employment of fanout also limits the density at which surface mounted components may be placed because fanout holes are occupying additional space on the top circuitry layer of the printed wiring board.
Some prior art methods for improving the routing density on printed wiring boards include the use of blind and buried vias. Blind vias are holes selectively drilled only in certain printed wiring board layers and enclosed by the printed wiring board stack up lamination process step. Buried vias simply refer to those blind vias that do not connect to either the top or bottom circuitry level, i.e., that are buried in the stack-up. This process permits the movement of a plated through hole from an undesirable position, but interconnection to the enclosed blind via still must be made by connecting the blind via to a plated through hole. Also, the layers with the blind vias must be predrilled and preplated prior to the lamination step thereby adding further complexity and cost to the fabrication process.
The typical processing of a printed wiring board starts with the step of printing and etching a conductor pattern on each individual printed wiring board laminate layer. The next step is to stack up the laminate layers with pre preg layers in between each laminate layer. The pre-preg layers basically act as a bonding surface between the laminate layers. The through holes are then drilled through the stack up in preparation for copper electroplating. After the separate electroplating step, the board is cured and laminated, completing the process.
Accordingly, it is an object of the present invention to provide an improved circuit board fabrication technique that alleviates the prior art problems outlined above particularly as they relate to plated through holes and printed wiring boards or printed circuit boards.
Another object of the present invention is to provide an improved printed circuit board construction that is of simplified form, that is less expensive than prior art circuit boards and that is substantially unaffected by temperature or other environmental variables.
A further object of the present invention is to provide a new method of constructing inter-level electrical connections in a printed circuit or wiring board, and in particular a method that greatly increases the routing density per unit area.
Still another object of the present invention is to provide a more simplified method for fabrication of printed wiring and/or printed circuit boards.